Integrated circuit chips are widely used in consumer, commercial and industrial applications. As is well known to those having skill in the art, integrated circuit chips generally are fabricated in integrated circuit wafers, which may comprise semiconductor materials. The wafers contain an array of scribe line regions that are arranged to provide a plurality of integrated circuit chips in the wafer. After fabrication, the integrated circuit wafer is diced along the scribe lines, to separate (singulate) the individual integrated circuit chips, which are then packaged for use.
As is well known to those having skill in the art, integrated circuit chips generally include internal circuits that include interconnected semiconductor devices such as transistors, diodes, capacitors, optical elements, optoelectronic elements, microelectromechanical (MEM) elements and/or other devices, which are configured to provide integrated circuit functionality, such as a memory device, a microprocessor, an electro optical device, an electromechanical device and/or other analog and/or digital integrated circuit functionality. The internal circuit may also include test circuits for testing the integrated circuit functionality, for example to test for proper operation of the memory device, microprocessor other integrated circuit functionality.
It is also known to provide a Test Element Group (TEG) in the integrated circuit wafer, to allow measuring of electrical characteristics of the semiconductor devices themselves. A TEG circuit may be used to measure electrical characteristics of the semiconductor devices, so that data that is obtained by measuring the TEG circuit during a TEG test may be used, for example, to solve process problems. For example, process problems may be discovered and solved by judging whether each process is carried out correctly using the measured electrical characteristics. In particular, the electrical characteristics of the semiconductor devices generally are not measured directly by measuring the interconnected semiconductor devices in the internal circuit. Rather, a TEG circuit is provided in the scribe area of the semiconductor wafer and/or as one or more discrete TEG chips at various locations in the semiconductor wafer. Since the TEG circuit is formed by the same process that is used to form the interconnected semiconductor devices in the internal circuit, the measure of electrical characteristics of the semiconductor devices in the TEG circuit can provide a measure of the electrical characteristics of the interconnected semiconductor devices in the internal circuit. Thus, electrical characteristics of the semiconductor devices in the chip can be obtained by testing the TEG circuits, i.e. by performing a TEG test.
TEG circuits have been used to test various electrical characteristics of semiconductor devices in an integrated circuit chip, such as the drain current of a transistor, the threshold voltage of an inverter, inter-metal open/short states, contact resistance, capacitance, and/or many other electrical characteristics. As was described above, data obtained through the TEG test may be utilized to estimate process reliability and/or stability. The TEG circuit can be formed in the scribe line regions of the wafer and/or in one or more separate TEG chips in the wafer. Various TEG circuits for measuring electrical characteristics of semiconductor devices in an integrated circuit chip are disclosed in Japanese Laid-Open Patent Application Nos. 2000-332077; 2000-31221; and Ser. No. 09-172049, and in Korean Patent Application Nos. 1997-53226 and 2000-51684. Other TEG circuits are described in U.S. Pat. Nos. 6,372,554; 6,368,943; 6,326,676; 6,326,309; 6,075,373; 5,936,420; and 5,650,961.
FIG. 11 is a flowchart illustrating conventional methods of fabricating and testing integrated circuit chips. As shown at Block S10, a plurality of integrated circuit chips, each including various internal circuits including interconnected semiconductor devices that are configured to provide integrated circuit functionality, are formed in a semiconductor wafer using well-known fabrication processes. Simultaneous with the fabrication of the internal circuits, a TEG circuit also is fabricated in the scribe line regions of the wafer and/or as one or more separate TEG chips in the wafer. Then, at Block S20, the TEG circuits are tested in order to measure electrical characteristics of the semiconductor devices in the internal circuits. An Electric Die Sorting (EDS) test is then performed on the internal circuits of the individual integrated circuit chips in the wafer, in order to determine which chips are properly performing their integrated circuit functionality. The EDS test generally is carried out using a tester that includes a probe card. The probe card includes probes such as needles and/or pins that electrically connect the tester to the chip or chips under test. The probes may be mounted on the probe card. Finally, referring to Block S40, after the EDS test, the good integrated circuit chips are assembled and packaged.
Unfortunately, conventional testing methods as illustrated in FIG. 11 may take an excessive time to perform the TEG test of Block S20 and the EDS tests of Block S30. Moreover, the TEG tests may produce inaccurate results, because the TEG circuits that are formed at the scribe line regions of the wafer and/or in separate TEG chips, may not be representative of the electrical characteristics of all of the integrated circuit chips in a wafer.